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PD - 94594D
IRF7832
HEXFET(R) Power MOSFET
Applications l Synchronous MOSFET for Notebook Processor Power l Synchronous Rectifier MOSFET for Isolated DC-DC Converters in Networking Systems Benefits l Very Low RDS(on) at 4.5V VGS l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage and Current l 20V VGS Max. Gate Rating
VDSS
30V
RDS(on) max
4.0m:@VGS = 10V
A A D D D D
Qg
34nC
S S S G
1
8 7
2
3
6
4
5
Top View
SO-8
Absolute Maximum Ratings
Parameter
VDS VGS ID @ TA = 25C ID @ TA = 70C IDM PD @TA = 25C PD @TA = 70C TJ TSTG Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current
Max.
30 20 20 16 160 2.5 1.6 0.02 -55 to + 155
Units
V
c
A W W/C C
Power Dissipation Power Dissipation Linear Derating Factor Operating Junction and Storage Temperature Range
Thermal Resistance
Parameter
RJL RJA Junction-to-Drain Lead Junction-to-Ambient
Typ.
--- ---
Max.
20 50
Units
C/W
f
Notes through are on page 10
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1
1/14/04
IRF7832
Static @ TJ = 25C (unless otherwise specified)
Parameter
BVDSS VDSS/TJ RDS(on) VGS(th) VGS(th) IDSS IGSS gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw Qoss td(on) tr td(off) tf Ciss Coss Crss Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Transconductance Total Gate Charge Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) Output Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. Typ. Max. Units
30 --- --- --- 1.39 --- --- --- --- --- 77 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 0.023 3.1 3.7 --- 5.7 --- --- --- --- --- 34 8.6 2.9 12 10.5 14.9 23 12 6.7 21 13 4310 990 450 --- --- 4.0 4.8 2.32 --- 1.0 150 100 -100 --- 51 --- --- --- --- --- --- --- --- --- --- --- --- --- pF VGS = 0V VDS = 15V ns nC nC VDS = 15V VGS = 4.5V ID = 16A S nA V mV/C A V m
Conditions
VGS = 0V, ID = 250A VGS = 10V, ID = 20A VGS = 4.5V, ID = 16A
V/C Reference to 25C, ID = 1mA
e e
VDS = VGS, ID = 250A VDS = 24V, VGS = 0V VDS = 24V, VGS = 0V, TJ = 125C VGS = 20V VGS = -20V VDS = 15V, ID = 16A
See Fig. 16 VDS = 16V, VGS = 0V VDD = 15V, VGS = 4.5V ID = 16A Clamped Inductive Load
= 1.0MHz
Avalanche Characteristics
EAS IAR Parameter Single Pulse Avalanche Energy Avalanche Current
d
Typ. --- ---
Max. 260 16
Units mJ A
Diode Characteristics
Parameter
IS ISM VSD trr Qrr ton Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)A Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- --- --- --- --- --- 41 39 3.1 A 160 1.0 62 59 V ns nC
Conditions
MOSFET symbol showing the integral reverse
G S D
p-n junction diode. TJ = 25C, IS = 16A, VGS = 0V TJ = 25C, IF = 16A, VDD = 10V di/dt = 100A/s
e
e
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRF7832
1000
TOP VGS 10V 5.0V 4.5V 3.5V 3.0V 2.7V 2.5V 2.25V
1000
TOP VGS 10V 5.0V 4.5V 3.5V 3.0V 2.7V 2.5V 2.25V
ID, Drain-to-Source Current (A)
100
ID, Drain-to-Source Current (A)
100
BOTTOM
10
BOTTOM
1
2.25V
0.1
10
2.25V 20s PULSE WIDTH Tj = 150C
1
20s PULSE WIDTH Tj = 25C
0.01 0.1 1 10 100 1000
0.1
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
RDS(on) , Drain-to -Source On Resistance
2.0
ID, Drain-to-Source Current ()
ID = 16A VGS = 4.5V
1.5
100
TJ = 150C
(Normalized)
10
1.0
T J = 25C
1
0.5
VDS = 15V 20s PULSE WIDTH
0 2.0 2.5 3.0 3.5 4.0
0.0 -60 -40 -20 0 20 40 60 80 100 120 140 160
VGS, Gate-to-Source Voltage (V)
T J, Junction Temperature (C )
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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IRF7832
100000 VGS = 0V, f = 1 MHZ Ciss = C + C , C SHORTED gs gd ds Crss = C gd Coss = Cds + Cgd
6
ID= 16A VDS= 24V VDS= 15V
VGS, Gate-to-Source Voltage (V)
100
5
C, Capacitance(pF)
10000
4
Ciss
3
1000
Coss Crss
2
1
100 1 10
0 0 10 20 30 40 50 VDS, Drain-to-Source Voltage (V) QG Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000
1000
ISD , Reverse Drain Current ( )
100
T J = 150C 10 T J = 25C 1
ID, Drain-to-Source Current (A)
100
100sec 10 1msec Tc = 25C Tj = 150C Single Pulse 1 1 10 VDS, Drain-to-Source Voltage (V)
VGS = 0V 0.1 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VSD , Source-to-Drain Voltage (V)
10msec 100
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRF7832
24
VGS(th) , Gate Threshold Voltage (V)
2.5
20
2.0
ID, Drain Current (A)
16
12
1.5
ID = 250A
8
1.0
4
0 25 50 75 100 125 150 T C , Case Temperature (C)
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160
T J , Temperature (C)
Fig 9. Maximum Drain Current Vs. Case Temperature
Fig 10. Threshold Voltage Vs. Temperature
100
D = 0.50
Thermal Response ( Z thJA )
10
0.20 0.10 0.05
1
0.02 0.01
0.1
SINGLE PULSE ( THERMAL RESPONSE )
0.01 1E-006 1E-005 0.0001 0.001 0.01 0.1 1 10 100
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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IRF7832
RDS(on), Drain-to -Source On Resistance (m )
10 ID = 20A 8
EAS , Single Pulse Avalanche Energy (mJ)
600
500
ID 7.0A 13A BOTTOM 16A TOP
400
6
TJ = 125C
300
4 TJ = 25C
200
2
100
0 2 3 4 5 6 7 8 9 10
0 25 50 75 100 125 150
V GS, Gate -to -Source Voltage (V)
Starting T J , Junction Temperature (C)
Fig 12. On-Resistance vs. Gate Voltage
Fig 13. Maximum Avalanche Energy vs. Drain Current
Current Regulator Same Type as D.U.T.
V(BR)DSS
15V
tp
12V .2F
50K .3F
VDS
L
DRIVER
D.U.T.
RG
20V VGS
+ V - DS
D.U.T
IAS tp
+ - VDD
A
VGS
0.01
I AS
3mA
Fig 14. Unclamped Inductive Test Circuit and Waveform
LD VDS
IG
ID
Current Sampling Resistors
Fig 15. Gate Charge Test Circuit
VDS
+
VDD D.U.T
90%
10%
VGS Pulse Width < 1s Duty Factor < 0.1%
VGS
td(on) tr td(off) tf
Fig 16. Switching Time Test Circuit
Fig 17. Switching Time Waveforms
6
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IRF7832
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test
V DD
VDD
+ -
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 18. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
Id Vds Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 19. Gate Charge Waveform
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IRF7832
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by; Synchronous FET The power loss equation for Q2 is approximated by;
* Ploss = Pconduction + P + Poutput drive
Ploss = Irms x Rds(on)
+ ( g x Vg x f ) Q
(
2
)
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
Q + oss x Vin x f + (Qrr x Vin x f ) 2
*dissipated primarily in Q1. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs' susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on.
Ploss = (Irms 2 x Rds(on ) ) Qgs 2 Qgd +I x x Vin x f + I x x Vin x f ig ig + (Qg x Vg x f ) + Qoss x Vin x f 2
This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage.
Figure A: Qoss Characteristic
8
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IRF7832
SO-8 Package Details
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IRF7832
SO-8 Tape and Reel
TERMINAL NUMBER 1
12.3 ( .484 ) 11.7 ( .461 )
8.1 ( .318 ) 7.9 ( .312 )
FEED DIRECTION
NOTES: 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
330.00 (12.992) MAX.
14.40 ( .566 ) 12.40 ( .488 ) NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25C, L = 2.0mH, RG = 25, IAS = 16A. Pulse width 400s; duty cycle 2%. When mounted on 1 inch square copper board.
Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.01/04
10
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